EDN

Static FPGA’s Can Take Advantage of Dynamic Reconfiguration

Instant on and ready to go can be a selling point when choosing an FPGA. A part that powers up ready to roll has some advantages over statically configured FPGA's that need to be loaded and ...
EDN

Power-aware FPGA design (Part 1)

Power consumption requirements in new autonomous, multimedia-savvy consumer products that can store, transmit, and receive data have catapulted system architects and board and chip designers into a ...
Electronics Weekly

Low power FPGA design: is it process or architecture?

Power consumption is becoming an increasingly important variable when it comes to calculating a carbon footprint for tele­com infrastructure projects. For example, on average, each fully loaded 3G ...
Electronic Design

Innovate for Low Power in A High-Performance FPGA

Traditionally, digital logic has not consumed significant static power, but this has changed dramatically as process nodes shrink. Leakage current in digital logic is now the primary challenge for ...
Electronic Design

Improve Logic Timing with Worst-Case Analysis

Worst-case circuit analysis (WCCA) is a cost-effective means of screening a design to verify with a high degree of confidence that potential defects and deficiencies are identified and eliminated ...
Design-Reuse

Synopsys steps up efforts in FPGA design tools

Synopsys steps up efforts in FPGA design tools By Michael Santarini, EE Times September 11, 2001 (2:21 p.m. EST) URL: http://www.eetimes.com/story/OEG20010911S0037 ...