Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Hackaday

Pocket-sized Test Pattern Generator Helps Check Those CRTs

Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based ...
Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
EDN

New test points slash ATPG test pattern count

Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...
Electronic Design

Using EDT Test Points to Reduce Test Time and Cost

The exponential growth in design sizes has rendered the traditional methods of design-for-test, layout, and timing closure no longer sufficient. Design and test engineers not only have to constantly ...