Semiconductor Engineering

Accelerating Design-For-Test Pattern Simulation

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

DDR Bus Simulator to solve BER contour simulation challenge

September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...
EDN

Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.
InfoWorld

Introduction to design patterns, Part 1: Design pattern history and classification

Get an overview of design patterns, then use what you've learned to evaluate whether the Composite pattern is a good choice for a particular Java use case Numerous strategies have been devised to ...